Your multi-radio IoT gateway passes individual RF tests—but when Wi-Fi and BLE run simultaneously, BLE connection drops every 15 seconds. After weeks of debugging, you discover the culprit: a noisy 26 MHz clock line from the LTE module coupling into the BLE crystal input.

In today’s compact, multi-protocol devices—combining Wi-Fi 6, BLE 5.3, LTE-M, NB-IoT, and GNSS—a poorly designed clock tree can silently degrade performance or cause intermittent failures. At ChipApex, we’ve helped clients fix these “ghost bugs” by treating clocks as critical RF signals, not just digital nets. In this guide, Senior FAE Mr. Hong reveals how to design a clean, low-jitter clock distribution system that keeps all radios happy.

Why Clock Quality Matters in Multi-Radio Systems

Each wireless protocol has strict timing requirements:

⚠️ Problem: A single noisy clock source—or poor routing—can desensitize receivers, increase packet loss, or break time sync.

Common Clock Tree Pitfalls

❌ 1. Sharing One Crystal Across Multiple ICs

• Looks cost-effective, but load capacitance mismatch causes frequency drift
• Each IC adds parasitic capacitance → crystal operates off-resonance
• Result: Frequency error >±50 ppm → LTE attach failure

❌ 2. Routing Clocks Parallel to RF or High-Speed Lines

• 26 MHz clock running next to Wi-Fi antenna feed = conducted/capacitive coupling
• Measured: +15 dB noise floor rise in BLE 2.4 GHz band

❌ 3. Using MCU Internal RC Oscillator for RF

• Internal RC: ±2% accuracy → fine for UART, fatal for RF protocols
• LTE requires ±0.1 ppm with network—impossible without external TCXO

❌ 4. Ignoring Ground Return Paths

• Clock traces over split ground planes → large loop area → EMI radiator
• Also picks up switching noise from DC-DC converters

Strategy 1: Choose the Right Clock Source per Function

✅ Pro Tip: Use dedicated crystals/XOs per radio unless the chipset explicitly supports sharing (e.g., ESP32-C6).

Strategy 2: Optimize PCB Layout for Clock Integrity

✅ Critical Rules:

1. Keep clock traces short (<25 mm preferred)
2. Route on top layer only, with solid ground plane underneath (no splits!)
3. Never route under RF components, antennas, or switching regulators
4. Add guard traces (ground) on both sides of high-frequency clocks (>20 MHz)
5. Use series resistor (22–100Ω) near source to damp ringing

📏 Example: A 26 MHz clock with 10 cm trace + no ground plane → measured jitter: 120 ps RMS
Same trace, 15 mm + solid GND → jitter: 3.2 ps RMS

Strategy 3: Use Clock Buffers When Distribution Is Needed

If one XO must drive multiple loads (e.g., Wi-Fi + application processor):

• Use a low-additive-jitter clock buffer:
  • CDCM1804 (TI): 30 fs RMS added jitter
  • Si5330x (Skyworks): programmable, <50 fs

[TCXO] → [Clock Buffer] ──→ LTE Modem  
                      ├─→ Wi-Fi SoC  
                      └─→ GNSS Module

💡 Benefits:

• Isolates load capacitance
• Provides matched trace lengths
• Reduces source loading → better stability

Real Case: Fixing Intermittent GNSS Fix Loss in Fleet Tracker

Client: Telematics device with LTE-M + GPS
Symptom: GPS loses fix every 2–3 minutes in urban areas
Root cause:

• Shared 26 MHz crystal between LTE modem and GPS
• LTE transmit bursts injected noise into crystal → GPS clock jitter ↑
• Measured GPS clock phase noise: -95 dBc/Hz @ 1 kHz offset (spec: <-120 dBc/Hz)

Solution:

1. Added dedicated 16.368 MHz TCXO for GPS (±0.5 ppm)
2. Replaced shared crystal with separate 38.4 MHz TCXO for LTE
3. Routed both clocks on top layer with ground guard rings
4. Added ferrite bead + 100 nF cap on GPS TCXO power

Result:

• GPS time-to-first-fix (TTFF): <28 sec (urban canyon)
• Zero fix loss in 30-day field test
• LTE throughput improved by 18% due to cleaner timing

All oscillators sourced via ChipApex with phase noise test reports.

Clock Source Selection Checklist

Before finalizing your BOM, ask:

• ☑ Does each radio have its own dedicated, spec-compliant clock source?
• ☑ Is the XO/TCXO’s phase noise verified at critical offsets (1 kHz, 10 kHz)?
• ☑ Are clock traces <25 mm, over solid ground, and away from noise sources?
• ☑ Is there a series damping resistor to prevent overshoot/ringing?
• ☑ Are power pins of oscillators filtered with LC or π-filter (not just 100 nF)?

Final Advice from Our FAE Team

“In multi-radio designs, your clock isn’t just a tick—it’s the heartbeat of every wireless conversation. Treat it like an RF signal, because it behaves like one.”
— Mr. Hong, Senior Field Application Engineer, ChipApex

Need Help with Low-Jitter Clock Design?

We supply:

• Low-phase-noise XO/TCXO (NDK, TXC, SiTime, Rakon)
• Clock buffers & dividers (TI, Skyworks, Renesas)
• FAE support: Send us your clock tree—we’ll review layout and recommend improvements
• Phase noise test data for critical frequencies

Contact Our FAE Team

About the Author

Mr. Hong is a Senior Field Application Engineer at ChipApex with over 12 years of experience in RF system design, signal integrity, and wireless coexistence. He has supported clients in telematics, smart city infrastructure, and industrial IoT in deploying reliable multi-protocol devices across EMEA and APAC. At ChipApex, he leads technical validation for timing components and advises on robust clock architecture for complex wireless systems.