2N7002DW

2N7002DW

$0.32
  • Description:MOSFET 2N-CH 60V 0.115A SC88
  • Series:-

SKU:1fe9e4f6df11 Category: Brand:

  
  • Quantity
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Product Detailed Parameters

  • Description:MOSFET 2N-CH 60V 0.115A SC88
  • Series:-
  • Mfr:onsemi
  • Package:Tape & Reel (TR),Cut Tape (CT)
  • Technology:MOSFET (Metal Oxide)
  • Configuration:2 N-Channel (Dual)
  • FET Feature:Logic Level Gate
  • Drain to Source Voltage (Vdss):60V
  • Current - Continuous Drain (Id) @ 25°C:115mA
  • Rds On (Max) @ Id, Vgs:7.5Ohm @ 50mA, 5V
  • Vgs(th) (Max) @ Id:2V @ 250µA
  • Gate Charge (Qg) (Max) @ Vgs:-
  • Input Capacitance (Ciss) (Max) @ Vds:50pF @ 25V
  • Power - Max:200mW
  • Operating Temperature:-55°C ~ 150°C (TJ)
  • Mounting Type:Surface Mount
  • Package / Case:6-TSSOP, SC-88, SOT-363
  • Supplier Device Package:SC-88 (SC-70-6)
  • Grade:-
  • Qualification:-

Download product information

2N7002DW

Buying Guide
Summary

onsemi 2N7002DW is a component in FET, MOSFET Arrays category typically evaluated for fit, operating limits, and supportability in production. Key specs include Description (MOSFET 2N-CH 60V 0.115A SC88), Packaging (Tape & Reel (TR), Cut Tape (CT)), Temperature (-55°C ~ 150°C (TJ)), Package/case (6-TSSOP, SC-88, SOT-363), and Mounting (Surface Mount).

Selection Notes
  • For 2N7002DW, ensure the supply current (115mA) is acceptable for battery life and thermal limits.
  • Confirm the operating temperature range (-55°C ~ 150°C (TJ)) meets your deployment conditions.
  • Verify FET Feature (Logic Level Gate) and compare it against your reference design limits.
  • Make sure the mounting type (Surface Mount) matches how the part will be installed and inspected.
Alternates & Substitutions
  • In FET, MOSFET Arrays designs, define acceptance criteria up front so alternates can be qualified and repeated in production.
  • Confirm the real operating corners (temperature -55°C ~ 150°C (TJ)) and avoid swaps that only work at typical conditions.
  • Keep the assembly and footprint constraints consistent (package/case 6-TSSOP, SC-88, SOT-363, supplier package SC-88 (SC-70-6), mounting Surface Mount) to avoid a late PCB change.
  • For production substitutions, confirm traceability and documentation expectations so the alternate can be released cleanly.
FAQ

How do I confirm compatibility for 2N7002DW?
Match mechanical footprint first, then verify electrical limits and operating conditions against your system constraints.

Can you confirm the Supplier Device Package for 2N7002DW?
SC-88 (SC-70-6)

Can you confirm the Vgs(th) (Max) @ Id for 2N7002DW?
2V @ 250µA

Which FET Feature is listed for 2N7002DW?
Logic Level Gate

Application Scenarios

When sourcing onsemi 2N7002DW for FET, MOSFET Arrays, engineers typically focus on de-risking integration and keeping validation repeatable. Good switch selection keeps losses and temperature rise predictable, which makes qualification and derating easier to defend. A robust switch choice reduces field risk by keeping thermal margins and fault behavior stable across production variance. Engineers generally treat gate drive, layout, and SOA as system-level constraints because they dominate switching behavior and EMI. In practice, within outdoor equipment, derating and PCB heat spreading determine long-term reliability under harsh environments. Across motor control and robotics, MOSFET stages must survive stalls and reversals, so SOA and transient strategy are validated under real waveforms. Across power adapters, switching stages balance conduction loss and switching loss, where gate drive and thermal design determine repeatability. In automotive modules, MOSFETs tolerate transients and inductive kickback while meeting EMI constraints on dense harnessed systems.

Compatibility Advice
  • For second-source planning, validate gate-drive loop inductance and Miller effects so switching does not trigger unintended turn-on. This keeps integration from depending on typical-only conditions.
  • To keep validation repeatable, confirm short-circuit and fault response behavior matches the system protection plan, because timing often dominates survivability during bring-up and production test.
  • In practice, validate dv/dt stress and Miller effects so switching does not trigger unintended turn-on under real parasitics before release to production.
Project Fit
  • Best fit when you can measure and verify onsemi 2N7002DW for FET, MOSFET Arrays integration in the final enclosure, when you can control layout parasitics so gate-drive behavior remains repeatable in production.
2N7002DW2N7002DW
$0.32
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